Topographies of Semiconductor Products

The Semiconductor Integrated Circuits Layout Design Act, 2000, has been enforced and Registry made operational with effect from May 1, 2011.

Protection

The Act, inter alia, provides for protection of Semiconductor Integrated Circuits Layout Designs by process of registration; mechanism for distinguishing layout designs which can be protected; prohibition of registration of layout designs which are not original or which have been commercially exploited for more than two years anywhere in India or in a Convention country or are not inherently distinctive or are not inherently capable of being distinguishable from any other registered layout design; payment of royalty for use of registered layout design and for innocent infringement.

Term of protection: ten years from filing of the application or first commercial exploitation.

Punishment for willful infringement are provided by imprisonment for a term which may extend to three years or with a fine not less than INR. 50,000 but not more than INR. 1,000,000 or both.

Assignment and transmission of the layout design is possible with or without the goodwill of the business concerned by the registered proprietor and registration of a user of a registered layout design. Further, the Act contemplates establishment of a Registry and an Appellate Board which, inter alia, shall hear and decide appeals from the orders of the Registrar.