Topographies of Semiconductor Products

– Law concerning Circuit Layout of Semiconductor Integrated Circuits of May 31, 1985, effective from January 1, 1986.

Membership in International Conventions

– None.

Filing

Application: to be filed with the Minister of International Trade and Industry. The clerical work in connection with the registration is performed by the “Japan Patent Cooperation Center” (JPCC).

Applicant: any individual or corporate body who has created a circuit layout, or his assignee.

Foreigners or nationals not living in the country: may obtain a registration for the establishment of a right to utilize a circuit layout without appointing a representative residing in Japan.

Utilization of the circuit layout prior to application: a registration cannot be obtained if the creator or a person authorized by him, performed as a business any act of assigning, leasing, displaying for the purpose of assignment or lease, or importing a semiconductor integrated circuit manufactured by using the circuit layout for which the application is being made, more than two years before the date of application.

Filing requirements for an application (to be sent to resident agent):

1. An application form stating the following matters:
(a) the name and domicile of the applicant and, in the case of a legal person, the name of his representative;
(b) the date of application;
(c) the date on which any act of assigning, leasing, displaying for the purpose of assignment or lease, or importing a semiconductor integrated circuit manufactured by using the relevant circuit layout (including products incorporating semiconductor integrated circuits therein) was first performed, if the act was performed as a business;
(d) the name and domicile of the creator of the circuit layout;
(e) the title/name of the semiconductor integrated circuit manufactured by using the relevant circuit layout;
(f) the classification of the semiconductor integrated circuit:
(i) constitution (e.g., Bipolar, MOS, Bi-MOS, CMOS);
(ii) technique (e.g., TTL, ECL, IIL);
(iii) function (e.g., Logic, Memory, Microcomputer, Linear); and (iv) brief explanation, if necessary (e.g., 8-bit single chip microcomputer).

2. Matters to be attached to the application form:
(a) documents explaining that the applicant is the creator;
(b) actual semiconductor integrated circuits (4 pieces), or one photograph showing such semiconductor integrated circuit, if the circuit layout applied for has not been transferred, leased, displayed or imported for business purposes prior to the filing date of application; (c) drawing(s) describing the circuit layout applied for, or photograph(s) showing such circuit layout.

3. Power of attorney (if a representative residing in Japan is appointed).

Examination

The application is examined only with respect to formality requirements.

Protection

Creation of a right to utilize a circuit layout: the right comes into force upon registration.

Duration: ten years from the date of registration.

Effects of the right: the owner of the right has the exclusive right to utilize, as a business, the circuit layout for which that right has been registered.

Limits of the right: the effect of the right shall not extend to (1) utilization of a circuit layout created by another person; (2) the act of manufacturing a semiconductor integrated circuit using a registered circuit layout for the purpose of analysis or evaluation; and (3) the act of assigning, leasing, displaying for the purpose of assignment or lease, or importing a semiconductor integrated circuit which has been assigned, when the owner of the right, an exclusive licensee, or a non-exclusive licensee assigns a semiconductor integrated circuit manufactured by using a registered circuit layout (including products incorporating such semiconductor integrated circuit therein).